// Copyright (C) 1953-2022 NUDT
// Verilog module name - announce_packet_process
// Version: V4.1.0.20221206
// Created:
//         by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
//         
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module announce_packet_process
(
    i_clk  ,
    i_rst_n,
	
    iv_data                               ,
	i_data_wr                             ,
    
	ov_data                               ,
	o_data_wr                             
);

// I/O
// clk & rst
input                   i_clk;
input                   i_rst_n; 
// pkt input                      ;
input	   [8:0]	    iv_data        ;
input	         	    i_data_wr      ;
// pkt output to NMA
output reg [8:0]	    ov_data        ;
output reg	            o_data_wr      ;               
//***************************************************
//              modify  dmac
//***************************************************  
reg        [3:0]        rv_byte_cnt ;
reg        [1:0]        rv_app_state;  
     
localparam              IDLE_S                              = 2'd0,
                        MODIFY_DMAC_S                       = 2'd1,
                        TRANS_PKT_S                         = 2'd2;   
always @(posedge i_clk or negedge i_rst_n) begin
    if(i_rst_n == 1'b0)begin
        o_data_wr             <= 1'b0;
        ov_data               <= 9'h0;

        rv_byte_cnt           <= 4'b0;        
        rv_app_state          <= IDLE_S;
    end
    else begin
        case(rv_app_state)
            IDLE_S: begin    				
                if(i_data_wr)begin
                    o_data_wr    <= i_data_wr;
                    ov_data      <= iv_data  ;
                    rv_byte_cnt  <= 4'd1     ;                       
					rv_app_state <= MODIFY_DMAC_S;
			    end
				else begin
					o_data_wr          <= 1'b0;
				    ov_data            <= 9'h0;
                    rv_byte_cnt        <= 4'd0;
					rv_app_state       <= IDLE_S;
				end
			end
            MODIFY_DMAC_S:begin//将TSMP目的MAC[11:0]修改为组播ID（12‘h700）.
				rv_byte_cnt  <= rv_byte_cnt + 1'b1     ; 
                if(rv_byte_cnt <= 4'd2)begin
					o_data_wr    <= 1'b1;
					ov_data      <= iv_data;
					rv_app_state <= MODIFY_DMAC_S;
			    end
                else if(rv_byte_cnt == 4'd3)begin
					o_data_wr    <= 1'b1;
					ov_data      <= 9'h070;
					rv_app_state <= MODIFY_DMAC_S;
			    end
                else if(rv_byte_cnt == 4'd4)begin
					o_data_wr    <= 1'b1;
					ov_data      <= 9'h000;
					rv_app_state <= MODIFY_DMAC_S;
			    end
                else if(rv_byte_cnt == 4'd5)begin
					o_data_wr    <= 1'b1;
					ov_data      <= 9'h000;
					rv_app_state <= TRANS_PKT_S;
			    end
                else begin
					o_data_wr    <= 1'b1;
					ov_data      <= iv_data;
					rv_app_state <= MODIFY_DMAC_S;
                end                
            end
			TRANS_PKT_S:begin
                ov_data      <= iv_data;
                o_data_wr    <= i_data_wr;            
                if(iv_data[8] == 1'b1)begin
                    rv_app_state <= IDLE_S;
				end
				else begin
                    rv_app_state <= TRANS_PKT_S;
				end
			end
            default:begin
				o_data_wr                     <= 1'b0;
				ov_data                       <= 9'h0;
                rv_app_state            <= IDLE_S;
            end
        endcase
    end
end
endmodule